"A few points that I'd like to note down from Chuck Moore's presentation since they're not written onto the slides:

- Bulldozer will have improved single-thread performance than today's processors
- He seems to imply that at some point SIMD instructions may be offload to GPU, but it'll be the (post-2011) future era
- Larger cache, higher memory integration (stacked memory) are being considered for the future era

- Llano has CPU and GPU sharing the same memory controller(s)
- Llano will use currently existing (OpenCL & DirectCompute) programming model
- Llano will have the video processing & display subsystem and integrated PCIe bus

- Bobcat core(s) can be integrated with GPU and/or other peripheral functions in the computer
- Future generations of Bobcat will continue to have even lower power

- Each Bulldozer module is an optimized dual core
- Each Bulldozer "core" is capable of 2 loads/cycle; each is a 4-way out-of-order machine
- Bulldozer module is not bigger in area than Intel's hyperthreading design
- Bulldozer module can achieve ~80% speedup when running 2 threads (versus ~25% from hyperthreading)
- Multiple Bulldozer modules can share the L2 cache; and multiple of those (module? L2?) can share the L3 and NB
- Each INT scheduler can issue 4 inst./cycle; the FP scheduler can issue 4 inst./cycle
- "Over time" a Bulldozer "core" (INT only?) can be deployed in APU to work with GPGPU (for FP?)

Conclusion: Each Bulldozer core is 4-way INT and 2 to 4-way FP (depending on sharing), up from the 3-way each in K8/K10 today."